Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reduction in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Many of the electronic systems that provide these advantageous results include oscillating electrical signals (e.g. clock signals, carrier signals, etc.). It is often important to accurately and rapidly regulate these oscillating signals (e.g., clock signals, carrier signals, etc).
Phase Lock Loops are widely used in many types of electronic circuits for controlling oscillating signals. For example, phase lock loops can be utilized to facilitate clock distribution, clock multiplication, skew suppression and a variety of other applications. Phase Lock Loops typically facilitate these activities by controlling a signal's phase and/or frequency. In some Phase Lock Loop applications, it is important to minimize the lock time (e.g., the time it takes the PLL to accomplish frequency and phase acquisition). Conventional Phase Lock Loops often alter loop bandwidth in an attempt to reduce lock time. However, changes in loop bandwidth can impact stability and thus conventional approaches often result in a trade off effect between lock time and stability. A high bandwidth loop usually results in a short lock time, but may compromise the loop stability (which in turn may itself impact the lock time). On the other hand a low bandwidth loop usually has a longer lock time. Conventional approaches often attempt to alter the bandwidth of the PLL by altering the loop filter dynamics temporarily, for example by varying the loop filter resistor and/or temporarily increasing the charge pump current.
FIG. 1 shows an exemplary conventional PLL circuit that modifies the PLL bandwidth by altering the magnitude of the charge pump current (i.e. Bandwidth (BW)αIcp) according to the state of a lock condition (i.e “locked” or “unlocked”). This type of conventional circuit usually includes a relatively complicated lock detector circuit 110. If the PLL is out of lock, the lock detector circuit 110 increases the loop bandwidth by increasing the charge pump 130 current from Icp1 to (Icp1+Icp2). This increased current is passed to the low pass filter 140 during each up refresh (UP) and down refresh (DN) from the phase frequency detector (PFD) 120. When the PLL is close to “locking” the feedback clock to the reference clock, the lock detector circuit reduces the loop bandwidth by switching to the lower charge pump current Icp1. Voltage controlled oscillator (VCO) 150 makes corresponding changes to an output signal which is fed back to a divider 170 and then to phase frequency detector (PFD) 120. Loop stability may be compromised by the increased bandwidth in such conventional approaches.